HFETs fabricated using III-V semiconductors have a variety of potential applications in the fields of high-speed logic, microwave and millimeter-wave circuits, and optoelectronics. The HFET differs from a homostructure FET in that the device structure includes materials with different band gaps to obtain higher performance levels which would otherwise be unattainable. The composition and doping of each material used in the structure can also be varied. This high degree of design freedom has resulted in HFETs which have significantly improved performance at increasingly high frequencies. Even though work on HFETs is relatively new, definite trends in device design for improved performance can be observed. One trend is the use of a material with a relatively wide-band gap (Al.sub.x Ga.sub.1-x As, In.sub.x Al.sub.1-x As, AlSb) together with a material with a relatively narrow-band gap (GaAs, In.sub.x Ga.sub.1-x As, InAs) to maximize the conduction band discontinuity within the structure. The wide-band gap material is also employed to obtain a quality Schottky-barrier gate characteristic. In the narrow band-gap material, there is a trend toward using increasingly high In mole fractions to increase the electron mobility and velocity within the device. A further trend is to use increasingly higher doping densities and very thin channels because this allows for improvement in the transconductance and the gate-channel aspect ratio (gate length/gate-channel distance) which together improve the high-frequency performance. When comparing an HFET to a homostructure FET, the two structures are quite different in the starting materials used. However, the fabrication process commonly reported for both cases is the same. Due to the trends indicated above, a different fabrication method may be necessary to fully exploit the improved performance potential in HFETs.
Limitations of conventional InP-based HFETs include excessive gate leakage current related to the low barrier height of the Schottky gate, low gate-drain breakdown voltage, low source-drain breakdown voltage, and high output conductance. These limitations have impeded the use of these devices in power amplifiers, where large breakdown voltages are required, or as low-noise amplifiers in photoreceivers, where low leakage current is essential.
A mesa etch is conventionally used at the beginning of an HFET process for the purpose of confining the electron flow between the source and the drain. This requires the gate metalization, which is formed later in the process, to traverse the mesa edge. As the gate metal traverses the mesa edge, it contacts the narrow-band gap material (FIG. 15). This has the effect of lowering the Schottky barrier height of the gate metal and significantly increases the reverse leakage current of the HFET.
In conventional HFETs, the mesa-edge region can also be the location where gate-drain and source-drain breakdown originates, due to the high localized fields which can occur here relative to other areas in the device. The high fields in this sidewall region can result from (1) the sharp change in the shape of the channel profile, (2) deleterious surface trapping effects which occur due to the mesa etch chemical process in conjunction with the exposed heterojunction layers at the sidewall, (3) deleterious surface trapping effects due to the dielectric passivation at the sidewall, and (4) deleterious metallic diffusion effects in this region which result from the ohmic contact alloy process. By surface trapping effects it is meant any effect at the material's surface which can alter charge profiles, and can be due, for example, to imcomplete surface bonds, contaminants, etc. Surface trapping in the gate-drain region can decrease the gate-drain breakdown potential, reducing the HEMT's operating voltage range.
HFETs with very high electron concentrations and thin channels have relatively low gate-drain and source-drain breakdown voltages because of the high fields generated, the close proximity of the highly-doped cap layer, and the influence of the surface potential in the gate-drain region. The surface potential in the vicinity of the gate plays a critical role in determining both gain and power performance, since it also affects the shape of the electric field in this region. An optimized surface potential can relax the field profile at the drain side of the gate and result in high breakdown voltages and lower output conductance. The surface potential is influenced by the total number and type of surface states which are present, and the contour of the surface profile in this region. The total number and type of surface states are determined by (first) the quality of the material at the start of the process, (second) the effects of chemical and physical processes which occur as a result of device processing prior to, during, and after the gate recess step, (third) the presence, or lack thereof, of a dielectric passivation layer covering this surface, and (fourth) the pretreatment of the surface prior to passivation, assuming that a passivation layer is employed.